The disclosed embodiments of the present invention relate to graphics processing, and more particularly, to a graphics processing circuit having a second vertex shader configured to reuse an output of a first vertex shader and/or process a repacked vertex thread group and related graphics processing method thereof.
Current graphics processing includes systems and methods developed to perform specific operations on graphics data. Traditionally, a graphics processing unit may only use fixed computational units to process the graphics data. More recently, a portion of the graphics processing unit may be implemented using programmable computational units to support a wider variety of operations. For example, a vertex shader may be made programmable.
In one conventional design, the vertex shading operation may be split into a first vertex shading stage and a second vertex shading stage. In general, the vertex shading operation includes multiple instructions. Though the vertex shading operation may be divided into two vertex shading stages, the instructions cannot be divided into two mutually exclusive instruction sets for the vertex shading stages. For example, instructions of the vertex shading operation contain first instructions, second instructions and third instructions. One instruction set executed by the first vertex shading stage may include the first instructions and the second instructions, while the other instruction set executed by the second vertex shading stage may include the first instructions and the third instructions. The conventional design of dividing the vertex shading operation into two vertex shading stages may allow the first vertex shading stage to skip the execution of the third instructions; however, the first instructions executed by the first vertex shading stage are needed to be executed by the second vertex shading stage again. As a result, the conventional design of dividing the vertex shading operation into two vertex shading stages is not efficient in instruction execution.